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74F543 Octal Registered Transceiver
April 1988 Revised March 1999
74F543 Octal Registered Transceiver
General Description
The F543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The A outputs are guaranteed to sink 24 mA while the B outputs are rated for 64 mA.
Features
s 8-bit octal transceiver s Back-to-back registers for storage s Separate controls for data flow in each direction s A outputs sink 24 mA s B outputs sink 64 mA
Ordering Code:
Order Number 74F543SC 74F543MSA 74F543SPC Package Number M24B MSA24 N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
(c) 1999 Fairchild Semiconductor Corporation
DS009554.prf
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74F543
Unit Loading/Fan Out
U.L. Pin Names OEAB OEBA CEAB CEBA LEAB LEBA A0-A7 Description HIGH/LOW A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-STATE Outputs B0-B7 B-to-A Data Inputs or A-to-B 3-STATE Outputs 1.0/1.0 1.0/1.0 1.0/2.0 1.0/2.0 1.0/1.0 1.0/1.0 3.5/1.083 150/40 (33.8) 3.5/1.083 600/106.6 (80) Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-1.2 mA 20 A/-1.2 mA 20 A/-0.6 mA 20 A/-0.6 mA 70 A/-650 A -3 mA/24 mA (20 mA) 70 A/-650 A -12 mA/64 mA (48 mA)
Functional Description
The F543 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0-A7 or take data from B0-B7, as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs.
Data I/O Control Table
Inputs CEAB H X L X L LEAB X H L X X OEAB X X X H L Latch Status Latched Latched Transparent -- -- Output Buffers High Z -- -- High Z Driving
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F543
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC 10% VCC VOL IIH IBVI Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test IBVIT ICEX VID IOD IIL IIH + IOZH IIL + IOZL IOS IZZ ICCH ICCL ICCZ Input HIGH Current Breakdown (I/O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current -0.6 -1.2 Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current 67 83 83 -60 -100 70 -650 -150 -225 500 100 125 125 A mA mA mA 0.0V Max Max Max A A mA Max Max Max mA Max 3.75 A 0.0 4.75 V 0.0 IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (OEAB, OEBA) VIN = 0.5V (CEAB, CEBA) VOUT = 2.7V (An, Bn) VOUT = 0.5V (An, Bn) VOUT = 0V (An) VOUT = 0V (Bn) VOUT = 5.25V (An, B n) VO = HIGH VO = LOW VO = HIGH Z 50 A Max VOUT = VCC 0.5 mA Max 10% VCC 10% VCC 2.5 2.4 2.7 2.7 2.0 0.5 0.55 5.0 7.0 A A Max Max V Min V Min Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA (An) IOH = -3 mA (An, Bn) IOH = -1 mA (An) IOH = -3 mA (An, Bn) IOH = -15 mA (Bn) IOL = 24 mA (A n) IOL = 64 mA (B n) VIN = 2.7V (OEAB, OEBA, LEAB, LEBA, CEAB, CEBA) VIN = 5.5V (An, Bn)
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74F543
AC Electrical Characteristics
TA = +25C Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL Propagation Delay Transparent Mode An to Bn or Bn to An Propagation Delay LEBA to An Propagation Delay LEAB to Bn Output Enable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn tPHZ tPLZ Output Disable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn 1.0 2.5 6.0 5.5 8.0 10.5 1.0 2.5 9.0 11.5 3.0 4.0 7.0 7.5 9.0 10.5 3.0 4.0 10.0 12.0 ns 4.5 4.5 4.5 4.5 8.5 8.5 8.5 8.5 11.0 11.0 11.0 11.0 4.5 4.5 4.5 4.5 12.5 12.5 12.5 12.5 ns ns 3.0 3.0 VCC = +5.0V CL = 50 pF Typ 5.5 5.0 Max 7.5 6.5 3.0 3.0 TA = 0C to +70C CL = 50 pF Min Max 8.5 7.5 ns Units
AC Operating Requirements
TA = +25C Symbol Parameter Min tS(H) tS(L) tH(H) tH(L) tW(L) Setup Time, HIGH or LOW An or Bn to LEBA or LEAB Hold Time, HIGH or LOW An or Bn to LEBA or LEAB Latch Enable, B to A or B to A Pulse Width, LOW 3.0 3.0 3.0 3.0 8.0 VCC = +5.0V Max TA = 0C to +70C Min 3.5 3.5 3.5 3.5 9.0 ns ns Max Units
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74F543
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24
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74F543
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Package Number N24A
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74F543 Octal Registered Transceiver
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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